71M6403 Datasheet, PDF (29/75 Pages) Teridian Semiconductor Corporation – Electronic Trip Unit

71M6403
Electronic Trip Unit
SEPTEMBER 2006
Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special
function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or
disabled by the enable bits in SFRs IEN0, IEN1, and IEN2.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6403, such as
the CE, DIO, EEPROM interface, comparators.
Interrupt Overview: When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 50. Once
interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return
from instruction, "RETI". When an RETI is performed, the processor will return to the instruction that would have been next when
the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of whether
the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the
hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. On the
next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address.
Interrupt response will require a varying amount of time depending on the state of the MPU when the interrupt occurs. If the MPU
is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In other cases, the response
time depends on the current instruction. The fastest possible response to an interrupt is 7 machine cycles. This includes one
machine cycle for detecting the interrupt and six cycles to perform the LCALL.
Special Function Registers for Interrupts:
Interrupt Enable 0 register (IE0)
MSB
EAL
WDT
ES0
ET1
EX1
Table 33: The IEN0 Register
LSB
ET0
EX0
Bit
IEN0.7
IEN0.6
IEN0.5
IEN0.4
IEN0.3
IEN0.2
IEN0.1
IEN0.0
Symbol
EAL
WDT
-
ES0
ET1
EX1
ET0
EX0
Function
EAL=0 – disable all interrupts
Not used for interrupt control
ES0=0 – disable serial channel 0 interrupt
ET1=0 – disable timer 1 overflow interrupt
EX1=0 – disable external interrupt 1
ET0=0 – disable timer 0 overflow interrupt
EX0=0 – disable external interrupt 0
Table 34: The IEN0 Bit Functions
Page: 29 of 75
© 2006 TERIDIAN Semiconductor Corporation
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