TDA7546 Datasheet, PDF (65/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

TDA7546
8
Application notes
Application notes
8.1
Typical RDS data transfer:
1. After power up the device, the PLL must be initialized and enabled to generate the 8.55
MHz or 8.664 MHz system clock (fsys). If the XTI frequency is already 8.55 MHz or
8.664 MHz, this point can be skipped. If not, the pllreg4-0 register must be programmed
via I²C/SPI. If the XTI frequency is smaller then 8.55 MHz, the reduced maximum
I²C/SPI speed must be considered. After the pllreg4-0 register has been programmed,
500 us and additional 25 XTI input clock cycles must be waited until the PLL is locked
and the system clock fsys is switched over to the PLL output clock. Then the next
I²C/SPI transfer is allowed with its maximum speed specified for the 8.55/8.664 MHz
system clock (fsys).
2. In the next I²C/SPI transfer the interrupt source will be set to “buffer not empty”
(itsrc[2:0] = 001) and a resynchronization should be forced (rds_int[5] = 1), to be sure
that the buffer is empty and not filled with spurious RDS data. To do this only an write
access to the first register rds_int is needed.
3. Now the pin INTN must be continuously checked for an interrupt (active low). If there is
an interrupt the five registers rds_int, rds_qu, rds_corrp, rds_bd_h and rds_bd_l must
be read out to get the RDS data. The next interrupt can not be expected before 22 ms.
4. If it is not possible to service the interrupt in time, then the RDS buffer can store up to
24 RDS bocks. If the buffer is full and the data could not be read before the next RDS
block, the “buffer overflow” flag (rds_corrp[0] = 1) will be set. In this case at least one
RDS block is missed. The “buffer overflow” flag is only cleared, if the whole RDS buffer
is read out.
If there is no pin available for checking the INTN pin, then it is possible to read out the RDS
data by I²C/SPI polling. Only the “buffer not empty” flag (rds_int[6]) can be used for that. If
rds_int[6] bit is set, the I²C/SPI transfer must be continued, until at least the four register
rds_qu, rds_corrp, rds_bd_h and rds_bd_l are read out.
This must be done until rds_int[6] bit is set to zero (last RDS block). It is possible that the last
RDS block is the same as the last but one RDS block. This is the case if just one RDS block
was stored in the RAM buffer. If they are identical, one of them can be skipped.
If another interrupt source is used instead of “buffer not empty” for the INTN pin, also the
polling mode must be used for reading out the whole RDS buffer, as described above.
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