TDA7546 Datasheet, PDF (35/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

TDA7546
Functional description
An address reset of the RAM buffer can be performed by writing a 1 to “ar_res” bit in rds_int
register, it also forces a resynchronization.
Figure 10 describes the different states of the buffer with corresponding flags values:
1. This is the reset state, read (Rp) and write pointer (Wp) pointing at the same location 0.
The buffer is empty.
2. After the first buffer write operation, Wp points to the last written data (0, it is not
incremented) and the flag “bne” (buffer not empty) is set.
3. After next buffer write operation, Wp points to the last written data (3, incremented
address).
4. After buffer read operation, Rp points to incremented address (data to be read on the
next read cycle), following the Wp. As soon as Rp reaches the Wp (of value 3), it is not
incremented to 4 and flag “bne” is reset. Rp never goes ahead the Wp.
5. If the buffer is full (i.e. 24 blocks have been written before any read), flag “bfull” is set. If
no read operation is performed, on next write operation “bovf” (buffer overflow) is set,
and each subsequent write operation will overwrite the oldest data of the RAM buffer.
Rp is moved in front of the Wp.
6. If the whole content of the buffer has already been read, subsequent read operation will
always read the last written location - Rp never goes ahead the Wp.
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