TDA7546 Datasheet, PDF (51/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

TDA7546
Software specifications
Table 37. rds_int register
rds_int
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
00 000 00 0
write bne ar_res synch itsrc2 itsrc1 itsrc0 int
r/w r r/w r r/w r/w r/w r
(1)
interrupt source
itsrc2
no interrupt
0
buffer not empty
0
buffer full
0
block A
0
block B
1
block D
1
TA
1
TA EON
1
itsrc1
itsrc0
0
0
01
10
11
00
01
10
11
Interrupt bit. It is set to one on every programmed interrupt. It is
reset by reading rds_int register. The inverted version is also
externally available on RDSINT pin.
itsrc[2:0] selects interrupt source (1).
Block A, B, D and TA, TA EON interrupts only if "synch" =1.
Synchronization information (refer to pages 28-29).
1: The module is already synchronized.
0: The module is synchronizing.
It is used to force a resynchronization. If it is set to one, the RDS
modules are forced to resynchronization state and the RAM buffer
address is reset.
This bit is reset automatically. It is read always as zero.
Buffer not empty.
1: At least one block is present in the RAM buffer.
0: The RAM buffer is empty.
rds_int, rds_bd_ctrl and pllreg4-0 write order.
This bit is only used in SPI mode and is read always as zero.
1: Update of rds_int, rds_bd_ctrl and pllreg4-0 with data shifted in.
0: No update of rds_int, rds_bd_ctrl and pllreg4-0.
(1) If the interrupt source is changed form block A, B,
D, TA, TA EON to another one "no interrupt" must be
set before to clear the previous interrupt acknowledge.
Table 38. rds_qu register
rds_qu
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0
0
0
0
0
0
0
0
qu3 qu2 qu1 qu0 blk1 blk0 e synz
r
r
r
r
r
r
r
r
(2)
block name
blk1
blk0
block A
0
0
block B
0
1
block C,C'
1
0
block D
1
1
It indicates if error correction was successful.
1: The syndrome was zero after error correction.
0: The syndrome did not become zero and therefore the error
correction was not successful.
1: Block E is detected. This indicates a paging block which is
deÞned in the RBDS speciÞcation used in the United States of
America.
0: An ordinary RDS block A, B, C, C« or D is detected, or no valid
syndrome was found.
Bit 0 of block counter (2).
bit 1 of block counter (2).
bit 0 of quality counter (3).
bit 1 of quality counter (3).
bit 2 of quality counter (3).
bit 3 of quality counter (3).
(2) If "syncw" =1 of rds_bd_ctrl register, the block counter in-
dicates the expected RDS block.
(3) qu[3...0] counts the number of bits (max.16) which are
marked as bad by the demodulator within each RDS block.
It could be used as a quality information, indicating the max-
imum number of bits which are allowed to be corrected.
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