TDA7546 Datasheet, PDF (33/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

TDA7546
Functional description
5.2.7
receiving bad signal is shorter than the decreasing time of the flywheel counter,
then the RDS will keep its synchronization and stores RDS data every 22ms.
Section 3:
After leaving the tunnel, the signal is getting better and the RDS will be
synchronized again as described in section 1.
RAM buffer
The RAM buffer can store up to 24 RDS blocks (rds_bd_h[7:0] and rds_bd_l[7:0]) with their
related information (rds_qu[7:0] and rds_corrp[7:0]) (Figure 7):
Figure 8. RAM buffer usage
INTERNAL REGISTERS
rds_int[7..0]
rds_qu[7..0] rds_corrp[7..0] rds_bd_h[7..0] rds_bd_l[7..0] rds_bd_ctrl[7..0] sinc4reg[7..0]
testreg[7..0]
pllreg4[7..0]
pllreg0[7..0]
write access
(external)
RAM BUFFER
(24 blocks)
read access
(internal)
SA_DATAOUT
(spi mode)
SDA_DATAIN
(i2c mode)
rds_int[7..0]
I2C/SPI SHIFT REGISTER
rds_qu[7..0] rds_corrp[7..0] rds_bd_h[7..0] rds_bd_l[7..0] rds_bd_ctrl[7..0] sinc4reg[7..0]
testreg[7..0]
pllreg4[7..0]
pllreg0[7..0]
After power up, or after resynchronization by setting “ar_res” rds_int[5] to one, incoming
RDS blocks are stored in the RAM buffer when synchronization has been established
(Figure 8.). But if the bit “syncw” rds_bd_ctrl[0] (refer to page 50) is cleared, every received
RDS block is stored, also without synchronization. This means if the RDS is not
synchronized, every received consecutive 26 RDS data bits are treated as a RDS block.
Figure 9. RAM buffer update depends on “syncw” bit rds_bd_ctrl[0]
Synchro-
1
nization flag
"synch"
0
Write to RAM
Buffer if
"syncw" = 1
Write to RAM
Buffer if
"syncw" = 0
RDS data
bits
Block A
Block B
time
time
time
Block C
time
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