TDA7546 Datasheet, PDF (27/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

TDA7546
Functional description
5.2
5.2.1
5.2.2
RDS decoder
Overview
The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip.
It recovers the inaudible RDS/RBDS information which are transmitted on most FM radio
broadcasting stations.
The oscillator frequency is 10.25MHz and is derived from the tuner. The fractional PLL must
be initialized through I²C/SPI interface to generate the internal 8.55 MHz or 8.664 MHz
reference clock (toll).
Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all
further processing is done in the digital. After filtering the highly over sampled output of the
A/D converter, the RDS/RBDS demodulator extracts the RDS data clock, RDS data signal
and the quality information. A next RDS/RBDS decoder will synchronize the bit wise RDS
stream to a group and block wise information. This processing includes an error detection
and error correction algorithm. In addition, an automatic flywheel control avoids overheads
in the data exchange between the RDS/RBDS processor and the host.
The device operates in accordance with the CENELEC Radio Data System (RDS)
specification EN50067.
Fractional PLL
Figure 4. Fractional PLL
Input
Divider
Phase
Comperator
& VCO
f(vco)
Output
Divider
Fractional
Divider
Mux
PLL Controller
The fractional PLL (Figure 4) is used to generate from the XTI input clock one of the two
possible system clocks (fsys) 8.55 MHz or 8.664 MHz. For this a setting for the input diver
27/68