TDA7546 Datasheet, PDF (30/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

Functional description
TDA7546
5.2.5
Group and block synchronization module
The group and block synchronization module has the following features:
– Hardware group and block synchronization
– Hardware error detection
– Hardware error correction, using quality bit information to indicate bad corrections
– Hardware synchronization flywheel
– TA, TAEON information extraction
– Reset by software “ar_res”, which resets also RAM buffer addresses and RDS
demodulator
Figure 6. Group and block synchronization diagram
RDSCLK
RDSDAT
RDSQAL
from RDS
Demodulator
Group & Block Synchronization Control Block
rds_bd_h,rds_bd_l
read only
RDSDAT(15:0)
rds_corrp
read only
Block
missed
rds_qu
read only
Q(3:0)
Syndrome register
S(9:0)
S(4:0)
CP(9:5)
Correction ^{Correct. pat.}
logic
Corrected
Data_OK
Syndrom zero
QU(0:3)
next
RDS
bit
new
Block
available
bit_int _{rds_int}
set
read/write
res
int
set
Quality bit counter
RDS block counter
ABH
DBH
BLOCK E detected
BLOCK A
BLOCK B
BLOCK D
AR_RES
TAEON
TA
This module is used to acquire group and block synchronization of the received RDS data
stream, which is provided in a modified shortened cyclic code. For theory and
implementation of modified shortened cyclic code and error correction, please refer to
CENELEC Radio Data System (RDS) specification EN50067.
Group and block synchronization module can detect and correct five bit error burst in the
data stream. If an error correction is done on a good quality marked RDS bit, the “data_ok”
bit rds_corrp[1] won’t be set (refer to page 49). Before error correction, the five MSBs of the
syndrome register are stored in the “cp” bits rds_corrp[7:3].
If the five LSBs of the syndrome register are zero, the “cp” pattern is used for error
correction. After that operation the syndrome must become zero for valid RDS data. The
type of error can be measured with the five “cp” bits in order to classify the reliability of the
correction. Each bit set within “cp” means that one bit was corrected.
The two RDS data bytes rds_bd_h[7:0] and rds_bd_l[7:0] are available at the I²C/SPI
interface together with status bits rds_corrp[7:0] and rds_qu[7:0] giving reliability information
of the data (refer to Figure 5). rds_int[7:0] bits are used for interrupt and group and block
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