TDA7546 Datasheet, PDF (53/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

TDA7546
Software specifications
Table 42. rds_bd_ctrl register
rds_bd_ctrl
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0
0
0
0
0
0
0
1
freq qsens1 qsens0 pllb1 pllb0 pllf
r/w r/w r/w r/w r/w r/w
shw syncw
r/w r/w
(5)
pllf
0
1
(6)
pllb1
0
0
1
1
lock time needed for 90 deg deviation
2 ms
10 ms
pllb0
lock time needed for 90 deg deviation
0
5 ms (reset status)
1
15 ms
0
35 ms
1
76 ms
Write into buffer if synchronized (refer to page 10-12) (8)
1: Write into buffer only if synchronized (reset value).
0: Write into buffer any incoming RDS block.
Select PLL time constants by software or hardware (8)
1: Software. Time constants are selected by pllb[1:0] respectively
pllf.
0: Hardware (reset value). Time constants automatically increase
after reset or resynchronization.
Set the 57 kHz pll time constant (5) (8).
Bit 0 of 1187.5 Hz pll time constant (6) (8).
Bit 1 of 1187.5 Hz pll time constant (6) (8).
Bit 0 of quality sensitivity (7) (8).
Bit 1 of quality sensitivity (7) (8).
Select internal master clock frequency (fsys):
1: 8.664 MHz.
0: 8.55 MHz (reset value).
(7) Select sensitivity of quality bit.
00: minimum (reset value)
11: maximum
(8) Bit 5 "ar_res" of rds_int register will clear the bits 0-
6 of the rds_bd_ctrl register.
Table 43. sinc4reg register
sinc4reg
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0
0
0
0
0
0
0
0
-
-
- --
-
-
-
r/w r/w r/w r/w r/w r/w r/w r/w
sinc4reg register is for internal use only. For application this register
must be always Þlled with zeros.
Table 44. testreg register
testreg
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0
0
0
0
0
0
0
0
-
-
- --
-
-
-
r/w r/w r/w r/w r/w r/w r/w r/w
testreg register is for internal use only. For application this register
must be always Þlled with zeros.
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