TDA7546 Datasheet, PDF (57/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

TDA7546
Software specifications
The registers are written in the following order:
rds_int[7:0], rds_bd_ctrl[7:0], sinc4reg[7:0], testreg[7:0], pllreg4[7:0], pllreg3[7:0],
pllreg2[7:0], pllreg1[7:0], pllreg0[7:0].
sinc4reg[7:0] and testreg[7:0] are dedicated for test and have to keep zero filled for
application.
Figure 14. I²C write operation example: write of rds_int and rds_bd_ctrl registers
SA
0
CSN 1
SDA
SCL
S
START
CONDITION
SLAVE ADDRESS
W ACK
rds_int[7:0]
rds_bd_ctrl[7:0]
P
ACK
ACK
STOP
CONDITION
Read transfer
Figure 15. I²C read transfer
S Slave address R A
from master to slave
from slave to master
rds_int
A rds_qu
A testreg A P
S = start condition
R = read mode
Slave address = 001000S ( where S is the level of the pin
SA_DATAOUT)
A = acknowledge bit
P = stop condition
13 bytes can be read at a time (please refer to the to the relevant sectionsfor the meaning of
each bit).
The master has the possibility to read less than 13 registers by not sending the
acknowledge bit and then generating a stop condition after having read the needed amount
of registers.
There are two typical read access:
– read only the first register rds_int to check the interrupt bit.
– read the first five registers rds_int, rds_qu, rds_corrp, rds_bd_h and rds_bd_l to
get the RDS data.
The registers are read in the following order:
rds_int[7:0], rds_qu[7:0], rds_corrp[7:0], rds_bd_h[7:0], rds_bd_l[7:0], rds_bd_ctrl[7:0],
sinc4reg[7:0], testreg[7:0], pllreg4[7:0], pllreg3[7:0], pllreg2[7:0], pllreg1[7:0], pllreg0[7:0].
Only the “bne” flag can be used for polling mode. There are two different ways to use this
mode, while the first one causes less bus traffic than the second:
1. Read only the first register rds_int to check the “bne” bit.
If “bne” bit is not set, the stop condition can be set, as shown in (Figure 17).
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