TDA7546 Datasheet, PDF (50/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

Software specifications
TDA7546
6.3
6.3.1
RDS decoder software specification
Programming through serial bus interface
The serial bus interface is used to access the different registers of the chip. It is able to
handle both I²C and
SPI transfer protocols, the selection between the two modes is done thanks to the pin CSN:
– if the pin CSN is high, the interface operates as an I²C bus.
– if the pin CSN is asserted low, the interface operates as a SPI bus.
In both modes, the device is a slave, i.e the clock pin SCL_CLK is only an input for the chip.
Depending on the transfer mode, external pins have alternate functions as following:
Table 35. External pins alternate functions
pin
function in SPI mode (CSN=0)
function in I²C mode (CSN=1)
SCL_CLK
SDA_DATAIN
SA_DATAOUT
CLK (serial clock)
DATAIN (data input)
DATAOUT (data output)
SCL (serial clock)
SDA (data line)
SA (slave address)
13 registers are available with read or read/write access:
Table 36. Registers description
register
access
rights
function
rds_int[7:0]
rds_qu[7:0]
rds_corrp[7:0]
rds_bd_h[7:0]
rds_bd_l[7:0]
rds_bd_ctrl[7:0]
sinc4reg[7:0]
testreg[7:0]
pllreg4[7:0]
pllreg3[7:0]
pllreg2[7:0]
pllreg1[7:0]
pllreg0[7:0]
read/write
read
read
read
read
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
interrupt source setting, synch., bne information
quality counter, actual block name
error correction status, buffer ovf information
high byte of current RDS block
low byte of current RDS block
frequency, quality sensitivity, demodulator pll settings
sinc4 filter settings (for internal use only)
test modes (for internal use only)
PLL control register 4
PLL control register 3
PLL control register 2
PLL control register 1
PLL control register 0
The meaning of each bit is described below:
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