TDA7546 Datasheet, PDF (55/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

TDA7546
Software specifications
Note:
Table 48. pllreg1 register
pllreg1
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1
1
0
0
0
0
1
0
MF1 MF0 FRA13 FRA12 FRA11 FRA10 FRA9 FRA8
r/w r/w r/w r/w r/w r/w r/w r/w
(10) Reset values are designed for 10.25 MHz XTI in-
put frequency.
bit 8 of fractional factor (10) (12).
bit 9 of fractional factor (10) (12).
bit 10 of fractional factor (10) (12).
bit 11 of fractional factor (10) (12).
bit 12 of fractional factor (10) (12).
bit 13 of fractional factor (10) (12).
bit 0 of PLL multiplication factor (10) (11) (12).
bit 1 of PLL multiplication factor (10) (11) (12).
Table 49. pllreg0 register
pllreg0
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1
0
0
0
0
0
0
0
FRA7 FRA6 FRA5 FRA4 FRA3 FRA2 FRA1 FRA0
r/w r/w r/w r/w r/w r/w r/w r/w
(11) MF values smaller than 9 are ignored, 9 is then
used internally.
bit 0 of fractional factor (10).
bit 1 of fractional factor (10).
bit 2 of fractional factor (10)
bit 3 of fractional factor (10).
bit 4 of fractional factor (10).
bit 5 of fractional factor (10).
bit 6 of fractional factor (10).
bit 7 of fractional factor (10).
(12) The registers pllreg3, pllreg2 and pllreg1 must be
written at once to be updated, i.e. if the I2C/SPI stops
after pllreg2, then these registers are not updated.
sinc4reg and testreg registers are dedicated for testing and are not described in this
specification.
Reset values of rds_qu, rds_corrp, rds_bd_h and rds_bd_l registers are not visible for the
programmer, because he can see only the copy of this registers in the RAM buffer after a
new RDS block was received.
The pllreg4-0 registers must be initialized first, before the RDS functionality can be used. If
the “PLLEN” bit of pllreg4 is set from zero to one, then the PLL will be initialized after
I²C/SPI transfer with the actual values of pllreg4-0. After the lock time the PLL switches
automatically over to the PLL output clock. The next I²C/SPI transfer is only allowed after the
lock time (500μs) and additional 25 XTI input clock cycles. If the “PLLEN” bit is set from one
to zero, the PLL will be stopped and the system clock is switched back to the XTI input clock
(after the I²C/SPI transfer). The next I²C/SPI transfer is then only allowed after 25 XTI input
clock cycles. This is to avoid any I²C/SPI communication during clock switching.
The registers pllreg3-1 can be only changed at once. If there are less then all three pllreg3-
1 registers written during a I²C/SPI transfer, then they will be not updated.
If the XTI input frequency is 10.25MHz, then only register pllreg4 must be programmed,
because the pllreg3-0 register reset values can be used without any modification.
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