TDA7546 Datasheet, PDF (58/68 Pages) STMicroelectronics – Multichip module for TMC tuner applications

Software specifications
TDA7546
Note:
Note:
If “bne” bit is set, the transfer must be continued by the I²C master, until at least the four
register rds_qu, rds_corrp, rds_bd_h and rds_bd_l are read out, then the I²C master is
allowed to set the stop condition (Figure 16). Then the whole Buffer must be read out,
by reading each time at least the five registers rds_int, rds_qu, rds_corrp, rds_bd_h
and rds_bd_l without interruption. This must be done until the “bne” bit is set to zero
(last RDS block).
2. If the I²C master is not able to handle the above protocol, it must read always at least
the first five registers rds_int, rds_qu, rds_corrp, rds_bd_h, rds_bd_l out independent if
“bne” is set or not (Figure 16). If the “bne” flag is set the whole RAM buffer must be
read out, by reading each time at least the five registers rds_int, rds_qu, rds_corrp,
rds_bd_h and rds_bd_l without interruption. This must be done until the “bne” bit is set
to zero (last RDS block).
In polling mode the interrupt flag “int” is just a indication that the wanted information is stored
within the RAM Buffer.
In polling mode it is possible that the last RDS data (rds_qu, rds_corrp, rds_bd_h and
rds_bd_l), which was read out as the “bne” flag was set to zero, is identical to the RDS data
before. This must be checked by the external micro controller by comparing the last received
2 RDS blocks. If they are identical, one of them can be skipped. (This is the case if just one
RDS block is stored in the RAM buffer).
Figure 16. I²C read access example 1: read of 5 bytes
SA
0
CSN 1
SDA
SCL
S
START
CONDITION
SLAVE ADDRESS
R ACK
rds_int[7:0]
ACK
rds_qu[7:0]
ACK
rds_corrp[7:0]
rds_bd_h[7:0]
ACK
ACK
rds_bd_l[7:0]
P
ACK
STOP
CONDITION
Figure 17. I²C read access example 2: read of 1 byte
SA
0
CSN 1
SDA
rds_int[7:0]
SCL
S
START
CONDITION
SLAVE ADDRESS
R ACK
ACK
P
STOP
CONDITION
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