STE2004 Datasheet, PDF (60/66 Pages) STMicroelectronics – 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2004
Table 23 Electrical Characteristics (continued)
AC OPERATION (continued)
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
SERIAL INTERFACE
F_SCLK
Clock Frequency
V_DD1 = 1.7V;
8
MHz
T_CYC
Clock Cycle SCLK
125
ns
T_PWH1 SCLK pulse width HIGH
60
ns
T_PWL1
SCLK Pulse width LOW
60
ns
T_S2
CS setup time
V_DD1 = 1.7V
40
ns
T_H2
CS hold time
50
ns
T_PWH2 CS minimum high time
50
ns
T_S3
SD/C setup time
30
ns
T_H3
SD/C hold time
30
ns
T_S4
SDIN setup time
30
ns
T_H4
SDIN hold time
40
ns
T_S5
SDOUT Access Time
30
ns
T_H5
SDOUT Disable Time vs. SCLK
0
20
ns
T_H6
SDOUT Disable Time vs. CS
0
20
ns
Figure 75. Serial interface Timing
t_S2
t_H2
t_PWH2
CS
t_S3
t_H3
D/C
SCLK
t_PWL1
t_WH1
t_S4
t_H4
t_CYC
t_S2
SDIN
SOUT
t_S5
t_H5
t_H6
LR0096
Notes: 1.
F_frame
=
f_--o---s---c-
960
2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V_IL and V_IH with
an input voltage swing of V_SS to V_DD
3. Cb is the capacitive load for each bus line.
4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
5. C_VLCD is the filtering CApacitor on VLCD
6. Trise and Tfall (30%-70%) -10ns
7. I²C bus AC Characteristics are tested by correlation
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