STE2004 Datasheet, PDF (35/66 Pages) STMicroelectronics – 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2004
Figure 47. 68000-series Parallel interface protocol in Reading Mode
CS
D/C
R/W
E
D0
to
D7
LR0082
Figure 48. 68000-series Parallel interface protocol in Reading Mode (Several Bytes)
CS
D/C
R/W
E
D0
to
D7
Note 1) Data Bus is configured in high impedence mode after evry RD rising edge
2) Always the same data is output on D0-D7
LR0046
4.3.4 8080-series parallel interface
If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or transmit data.
While CS pin is high the 8080 Parallel interface is kept in reset.
Write Mode
Data are latched on WR rising edge.
Read Mode
Data are output on D0-D7 bus on RD rising edge. Data Bus is set in high impedance mode when RD is set to
logic 1.
Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus.
Figure 49. 8080-series parallel bus protocol - one byte transmission
CS
D/C
RD
WR
D0
to
D7
LR0083
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