STE2004 Datasheet, PDF (11/66 Pages) STMicroelectronics – 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2004
Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)¹
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
0123
98 99 100 101
LR0049
Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)¹
0123
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
98 99 100 101
LR0050
Figure 10. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)¹
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
101 100 99 98
3210
LR0051
Figure 11. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)¹
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
101 100 99 98
1. X Carriage=101; Y-Carriage = 8
3210
LR0052
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