STE2004 Datasheet, PDF (10/66 Pages) STMicroelectronics – 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2004
3.8 Display Data RAM
The STE2004, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0
to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access is accomplished
in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal)
and Y0 to Y8 (Vertical).
When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the mem-
ory map. The X pointer is increased after each byte written. After the last column address (X=X-Car-
riage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 8)
• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory
map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage),
X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 9).
• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the
memory map. The X pointer is increased after each byte written. After the last column address (X=X-
Carriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 10).
• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the mem-
ory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Car-
riage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 11).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the
cell with address (X;Y) = (0;0) (Fig. 12,13,14 & 15).
Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.16) or on the bottom (D0=1, Fig.
17).
The STE2004 provides also means to alter the normal output addressing. A mirroring of the Display along
the X axis is enabled setting to a logic one MY bit.This function doesn't affect the content of the memory
map. It is only related to the memory read process.
When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled.
When ICON MODE=0 the Icon Row is like an other graphic line and is mirrored and scrolled.
Three are the multiplex ratio available when the partial display mode is disabled (MUX 33, MUX 49 and
MUX 65). Only a subset of writable rows are output on Row drivers in MUX 33,49 & 65 Mode.
When Y-Carriage<MUX/8, if Mux 49 is selected only the first 49 memory rows are visualized; if Mux 33 is
selected only the first 33 memory rows are visualized. The unused output row & column drivers must be
left floating.
When Y-Carriage<=MUX/8 the icon Bank is located to BANK 8 in MUX 65 Mode, to BANK6 in MUX 49
Mode and to BANK 4 in MUX 33 Mode.
In Mux 33 & 49 Mode, when Y-Carriage>MUX/8 lines only 33, 49 lines are visualized.
It is possible to select which lines of DDRAM are connected on the output drivers using the scrolling func-
tion (Range: 0-Y-Carriage*8). When Y-Carriage>MUX/8 lines, the icon row is moved in DDRAM to the
first row of the Bank correspondant to Y-CARRIAGE Return value, being always connected on the same
output Driver.
When MY=0, the icon Row is output on R64 in mux 65 mode, on R56 in MUX 49 and on R48 in MUX33.
When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate.
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