STE2004 Datasheet, PDF (29/66 Pages) STMicroelectronics – 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

STE2004
the eighth SCLK clock pulse during every byte transfer.
If CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte
at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared.
If CS is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SDOUT can be read the driver I²C slave address or the status byte. The Command sequence that
allows to read I²C slave address or Status byte is reported in Fig. 34 & 35. SDOUT is in High impedance in
steady state and during data write.
It is possible to short circuit SDOUT and SDIN and read I2C address or status Byte without any additional lines.
Figure 34. 4-lines serial bus protocol - one byte transmission
CS
D/C
SCLK
SDIN
MSB
Figure 35. 4-lines serial bus protocol - several byte transmission
LSB
LR0071
CS
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
LR0072
Figure 36. 4-lines serial bus protocol - I2C Address or Status Byte Read
CS
SCLK
SDIN
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ^{Don't Don't Don't Don't Don't Don't Don't Don't}
Care Care Care Care Care Care Care Care
D/C
SDOUT
High-Z
High-Z
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ID Number
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
STATUS BYTE
Command Write
DATA Read
High-Z
High-Z
LR00076
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