LSM330D Datasheet, PDF (55/66 Pages) STMicroelectronics – Low power mode

LSM330D
Register descriptions
Table 75.
0110
0111
1000
1001
High-pass filter cut-off frequency configuration [Hz] (continued)
0.09
0.18
0.45
0.9
0.045
0.09
0.18
0.45
0.018
0.045
0.09
0.18
0.009
0.018
0.045
0.09
8.29
CTRL_REG3_G (22h)
Table 76.
I1_Int1
CTRL_REG3_G register
I1_Boot H_Lactive PP_OD
I2_DRDY
I2_WTM
I2_ORun I2_Empty
Table 77.
I1_Int1
I1_Boot
H_Lactive
PP_OD
I2_DRDY
I2_WTM
I2_ORun
I2_Empty
CTRL_REG3_G description
Interrupt enable on INT1_G pin. Default value 0. (0: Disable; 1: Enable)
Boot status available on INT1_G. Default value 0. (0: Disable; 1: Enable)
Interrupt active configuration on INT1_G. Default value 0. (0: High; 1:Low)
Push-pull / Open drain. Default value: 0. (0: Push-pull; 1: Open drain)
Date ready on DRDY_G/INT2_G. Default value 0. (0: Disable; 1: Enable)
FIFO watermark interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Ena-
ble)
FIFO overrun interrupt on DRDY_G/INT2_G Default value: 0. (0: Disable; 1: Enable)
FIFO empty interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Enable)
8.30 CTRL_REG4_G (23h)
Table 78. CTRL_REG4_G register
BDU
BLE
FS1
FS0
-
0
0
SIM
Table 79.
BDU
BLE
FS1-FS0
SIM
CTRL_REG4_G description
Block data update. Default value: 0
(0: continuous update; 1: output registers not updated until MSb and LSb
reading)
Big/little endian data selection. Default value 0.
(0: Data LSb @ lower address; 1: Data MSb @ lower address)
Full scale selection. Default value: 00
(00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)
3-wire SPI Serial interface read mode enable. Default value: 0
(0: 3-wire Read mode disabled; 1: 3-wire read enabled).
Doc ID 022562 Rev 2
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