LSM330D Datasheet, PDF (40/66 Pages) STMicroelectronics – Low power mode

Register mapping
LSM330D
Table 18. Register address map (continued)
Name
Slave
address
Type
Register address
Hex
Binary
TIME_LATENCY_A
Table 16 rw
3C
011 1100
TIME_WINDOW_A
Table 16 rw
3D
Act_THS
Table 16 rw
3E
011 1101
011 1110
Act_DUR
Table 16 rw
3F
011 1111
Reserved
Table 17 -
00-1E
-
WHO_AM_I_G
Table 17 rw
0F
0001111
Reserved
CTRL_REG1_G
Table 17 rw
Table 17 rw
10-1F
20
-
010 0000
CTRL_REG2_G
Table 17 rw
21
010 0001
CTRL_REG3_G
Table 17 rw
22
010 0010
CTRL_REG4_G
Table 17 rw
23
CTRL_REG5_G
Table 17 r
24
010 0011
010 0100
REFERENCE_G
Table 17 r
25
010 0101
OUT_TEMP_G
Table 17 r
26
010 0110
STATUS_REG_G
Table 17 r
27
010 0111
OUT_X_L_G
Table 17 r
28
010 1000
OUT_X_H_G
Table 17 r
29
010 1001
OUT_Y_L_G
Table 17 r
2A
010 1010
OUT_Y_H_G
Table 17 r
2B
010 1011
OUT_Z_L_G
Table 17 rw
2C
OUT_Z_H_G
Table 17 r
2D
010 1100
010 1101
FIFO_CTRL_REG_G
Table 17 rw
2E
010 1110
FIFO_SRC_REG_G
Table 17 r
2F
010 1111
INT1_CFG_G
Table 17 rw
30
000 0000
INT1_SRC_G
Table 17 rw
31
INT1_TSH_XH_G
Table 17 rw
32
011 0001
011 0010
INT1_TSH_XL_G
Table 17 rw
33
011 0011
INT1_TSH_YH_G
Table 17 rw
34
011 0100
INT1_TSH_YL_G
Table 17 rw
35
INT1_TSH_ZH_G
Table 17 rw
36
011 0101
011 0110
INT1_TSH_ZL_G
Table 17 rw
37
011 0111
INT1_DURATION_G
Table 17 rw
38
011 1000
Default
Comment
00000000
00000000
00000000
00000000
-
11010100
-
00000111
00000000
00000000
00000000
00000000
00000000
Output
Output
Output
Output
Output
Output
Output
Output
00000000
Output
Output
Output
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Reserved
40/66
Doc ID 022562 Rev 2