LSM330D Datasheet, PDF (47/66 Pages) STMicroelectronics – Low power mode

LSM330D
Register descriptions
Table 39. FIFO mode configuration
FM1
FM0
0
0
0
1
1
0
1
1
Bypass mode
FIFO mode
Stream mode
Trigger mode
FIFO mode
8.13
FIFO_SRC_REG_A (2Fh)
Table 40. FIFO_SRC_REG_A register
WTM OVRN_FIFO EMPTY
FSS4
FSS3
FSS2
FSS1
FSS0
Table 41. FIFO_SRC_REG_A description
WTM
WTM bit is set high when FIFO content exceeds watermark level
OVRN_FIFO
OVRN bit is set high when FIFO buffer is full, this means that the FIFO buffer
contains 32 unread samples. At the following ODR a new sample set replaces the
oldest FIFO value. The OVRN bit is reset when the first sample set has been read
EMPTY
EMPTY flag is set high when all FIFO samples have been read and FIFO is empty
FSS4-0
FSS[4:0] field always contains the current number of unread samples stored in the
FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until
the buffer is full, whereas, it decreases every time that one sample set is retrieved
from FIFO
8.14
INT1_CFG_A (30h)
Table 42. INT1_CFG_A register
AOI 6D ZHIE/
ZUPE
ZLIE/
ZDOWNE
YHIE/
YUPE
YLIE/
YDOWNE
XHIE/
XUPE
XLIE/
XDOWNE
Table 43.
AOI
6D
ZHIE/
ZUPE
ZLIE/
ZDOWNE
INT1_CFG_A description
And/Or combination of interrupt events. Default value: 0. Refer to Table 44: Inter-
rupt mode, “Interrupt mode”
6 direction detection function enabled. Default value: 0. Refer to Table 44: Interrupt
mode
Enable interrupt generation on Z high event or on direction recognition. Default
value: 0 (0: disable interrupt request;1: enable interrupt request)
Enable interrupt generation on Z low event or on direction recognition. Default
value: 0 (0: disable interrupt request;1: enable interrupt request)
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