VS6663CC Datasheet, PDF (41/63 Pages) STMicroelectronics – 1.3 megapixel camera module

VS6663CC
Video timing
6.2
Video timing
This section specifies the timing for the image data that is readout from the pixel array and
the output image data. These are not necessarily the same size.
The application of all of the video timing read/write parameters must be re-timed to the start
of frame boundary to ensure that the parameters are consistent within a frame. The video
stream which is output from the VS6663CC contains both video data and other auxiliary
information.
6.2.1
PLL block
The VS6663CC contains a phase locked loop (PLL) block, which generates all the
necessary internal clocks from the external clock input. Changes to the PLL settings on the
VS6663CC will only be consumed on the software standby to streaming mode transition.
Figure 16 shows the internal functional blocks, which define the relationship between the
external input clock frequency and the pixel clock frequency.
The majority of the logic within the device is clocked by vt_sys_clk however the CCI block is
clocked by the external input clock.
Figure 16. Clock relationship
External input clock
PLL input clock
ext_clk_freq_mhz pll_ip_clk_freq_mhz
PLL output clock
Video timing system clock Video timing pixel clock
pll_op_clk_freq_mhz vt_sys_clk_freq_mhz vt_pix_clk_freq_mhz
Ext.
input
clock
Max. _{pre_pll_}
27 MHz _{clk_div}
Max. _{pll_multiplier} Max.
12 MHz
800 MHz
Min. Range
6 MHz 1, 2, 4
Min. Min. _Max. Min.
6 MHz 25 ₁₃₃ 300 MHz
vt_sys_clk
_div
Max.
800 MHz⁽²⁾
vt_pix_clk ^Max.
_div
80 MHz
Range
1, 2, 4
Min.
Min. Max. Min.
75 MHz⁽¹⁾
8
10 ^{7.5 MHz}
1. The minimum vt_sys_clk_freq_mhz is 80 MHz in CSI-2 mode.
2. The maximum vt_sys_clk_freq_mhx is 640 MHz in CCP mode.
The equation relating the input clock frequency to pixel clock frequencies is:
vt_pix_clk_freq_mhz = _p----_r--_e---_{_}---_p----_l-_l--_{_}--^e-_c---^xl-_k--^t-_{__}----_dc---^li-^kv---^_--_×-^f--^r--_ve---_tq-_{_}---^_-_s--^m-_y---_s-^h--_{_}-^z--_c---^×_l-_k---_{_}-^p---_dl-^l--^_i-_v--^m---_×--^u---_vl--^t-_ti-_{_}-^p---_pl-ⁱ--^ei-_x--^r-_{_}----_c---_l-_k---_{_}---_d----_i-_v-
6.2.2
Framerate
The framerate of the array readout and therefore the output framerate is governed by the
line length, frame length and the video timing pixel clock frequency.
• line length is specified as a number of pixel clocks, line_length_pck
• frame length is specified as a number of lines, frame_length_lines
• video timing pixel clock is specified in MHz, vt_pix_clk_freq_mhz
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