VS6663CC Datasheet, PDF (14/63 Pages) STMicroelectronics – 1.3 megapixel camera module

Functional description
VS6663CC
3.2.1
Power-up procedure
The digital and analog supply voltages can be powered up in any order, for example, VDIG
then VANA or VANA then VDIG.
On power-up the on-chip power-on reset cell ensures that the CCI register values are
initialized correctly to their default values.
The EXTCLK clock can either be initially low and then enabled during software standby
mode or EXTCLK can be a free running clock.
The power-up sequence timing constraints are shown in Table 6.
Table 6. Power-up sequence timing constraints
Symbol
Parameter
Min.
Max.
Units
t0
VANA rising – VDIG rising
t1
VDIG rising – VANA rising
VANA and VDIG may rise in any
ns
order. The rising separation can
vary from 0 ns to indefinite.
ns
t2
VDIG / VANA rising –
XSHUTDOWN rising
t3
XSHUTDOWN – First I²C
transaction
XSHUTDOWN must rise later
than or coincident with the later
µs
rising supply (VDIG or VANA)
2400
-
EXTCLK cycles
t4
Minimum number of EXTCLK cycles
prior to the first I²C transaction
2400
-
EXTCLK cycles
t5
PLL start up/lock time
-
1
ms
t6
Entering streaming mode – First
frame start sequence (fixed part)
-
ms
t7
Entering streaming mode – First
frame start sequence (variable part)
= Integration time
The delay is the coarse
integration time value.
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