VS6663CC Datasheet, PDF (31/63 Pages) STMicroelectronics – 1.3 megapixel camera module

VS6663CC
Camera control interface (CCI)
4.2.12
Video timing parameter limit registers [0x1100 to 0x11FF]
For a full description of the video timing parameter limit registers refer to Chapter 6: Video
timing on page 38.
Table 21. Video timing parameter limit registers [0x1100 to 0x11FF]
Index Byte
Register name
Data type Default Type
Comment
0x1100 Hi
0x1101 3rd
min_ext_clk_freq_mhz
0x1102 2nd
0x1103 Lo
32SF
40.C0
00.00
Minimum external clock frequency
RO Units: MHz
Value: 6.0
0x1104 Hi
0x1105 3rd
max_ext_clk_freq_mhz
0x1106 2nd
0x1107 Lo
32SF
41.D8
00.00
Maximum external clock frequency
RO Units: MHz
Value: 27.0
0x1108 Hi
min_pre_pll_clk_div
0x1109 Lo
16UI
Minimum Pre PLL divider value
00.01 RO
Value: 1
0x110A Hi
max_pre_pll_clk_div
0x110B Lo
16UI
Maximum Pre PLL divider value
00.04 RO
Value: 4
0x110C Hi
0x110D 3rd
min_pll_ip_freq_mhz
0x110E 2nd
0x110F Lo
0x1110 Hi
0x1111 3rd
max_pll_ip_freq_mhz
0x1112 2nd
0x1113 Lo
0x1114 Hi
min_pll_multiplier
0x1115 Lo
32SF
40.C0
00.00
Minimum PLL input clock frequency
RO Units: MHz
Value: 6.0
32SF
41.40
00.00
Maximum PLL input clock frequency
RO Units: MHz
Value: 12.0
16UI
Minimum PLL multiplier
00.19 RO
Value: 25
0x1116 Hi
max_pll_multiplier
0x1117 Lo
16UI
Maximum PLL multiplier
00.85 RO
Value: 133
0x1118 Hi
0x1119 3rd
min_pll_op_freq_mhz
0x111A 2nd
0x111B Lo
32SF
43.96
00.00
Minimum PLL output clock
frequency
RO _{Units: MHz}
Value: 300.0
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