VS6663CC Datasheet, PDF (32/63 Pages) STMicroelectronics – 1.3 megapixel camera module

Camera control interface (CCI)
VS6663CC
Table 21. Video timing parameter limit registers [0x1100 to 0x11FF] (continued)
Index Byte
Register name
Data type Default Type
Comment
0x111C Hi
0x111D 3rd
max_pll_op_freq_mhz
0x111E 2nd
0x111F Lo
0x1120
0x1121
Hi
min_vt_sys_clk_div
Lo
0x1122
0x1123
Hi
max_vt_sys_clk_div
Lo
0x1124 Hi
0x1125 3rd
min_vt_sys_clk_freq_mhz
0x1126 2nd
0x1127 Lo
0x1128 Hi
0x1129 3rd
0x112A 2nd ^{max_vt_sys_clk_freq_mhz}
0x112B Lo
0x112C Hi
0x112D 3rd
min_vt_pix_clk_freq_mhz
0x112E 2nd
0x112F Lo
0x1130 Hi
0x1131 3rd
max_vt_pix_clk_freq_mhz
0x1132 2nd
0x1133 Lo
32SF
16UI
16UI
32SF
32SF
32SF
44.48
00.00
Maximum PLL output clock
frequency
RO _{Units: MHz}
Value: 800.0
00.01
00.04
42.96
00.00
44.48
00.00
Minimum video-timing system clock
RO ^{divider value}
Value: 1
Maximum video-timing system clock
RO ^{divider value}
Value: 4
Minimum video-timing system clock
frequency
RO ^{Units: MHz}
Value: 75.0
This value is 80 MHz in CSI2 mode.
Maximum video-timing system clock
frequency
Units: MHz
RO
Value: 800.0
The maximum value is 640 MHz in
CCP mode.
40.F0
00.00
Minimum video-timing pixel clock
frequency
RO _{Units: MHz}
Value: 7.5
32SF
42.A0
00.00
Maximum video-timing pixel clock
frequency
RO _{Units: MHz}
Value: 80.0
0x1134
0x1135
Hi
min_vt_pix_clk_div
Lo
16UI
00.08
Minimum video-timing pixel clock
RO ^divider
Value: 8
0x1136
0x1137
Hi
max_vt_pix_clk_div
Lo
0x1140
0x1141
Hi
min_frame_length_lines
Lo
16UI
16UI
00.0A
Maximum video-timing pixel clock
RO ^divider
Value: 10
00.D0
Minimum frame length allowed.
RO Value = 208
Units: Lines
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