VS6663CC Datasheet, PDF (19/63 Pages) STMicroelectronics – 1.3 megapixel camera module

VS6663CC
Functional description
3.2.3
Internal power-on reset (POR)
The VS6663CC internally performs a power-on reset (POR) when the digital supply rises
through the trigger level, Vtrig_rising. Similarly, if the digital power supply falls through the
trigger level, Vtrig_falling, then the power-on reset will also trigger.
Figure 10. POR timing
Burst <> t5
Burst < t4
Burst > t2
Burst > t5
Digital
Power
Supply,
VDIG
Vtrig_rising
Vtrig_falling
t1
POR Cell Output
t3
t1
Table 8. POR cell characteristics
Symbol
Constraint
Minimum Typical Maximum Units
t1
VDIG rising crossing Vtrig_rising – Internal reset
being released.
20.7
30.7
50.7
µs
Minimum VDIG spike width below Vtrig_falling
t2
which is considered to be a reset when POR cell 1.25
2.1
6.9
µs
output high.
t3⁽¹⁾
VDIG falling crossing Vtrig_falling - Internal reset
active.
1.25
2.1
6.9
µs
Minimum VDIG spike width below Vtrig_falling
t4
which is considered to be a reset when POR cell
1.5
2.1
6.9
µs
output low.
Minimum VDIG spike width above Vtrig_rising
which is considered to be a supply is stable when
t5
POR cell output low. While the POR cell output is 20.7
30.7
50.7
ns
low, all VDIG spikes above Vtrig_rising which are
less than t5 must be ignored.
Vtrig_rising VDIG rising trigger voltage.
429
755
944
mV
Vtrig_falling VDIG falling trigger voltage.
401
725
904
mV
1. The device could be reset by any VDIG voltage excursion falling below Vtrig_falling and will always be reset by a VDIG
voltage excursion below Vtrig_falling of > 0.5 µs
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