LPS35HW Datasheet, PDF (36/48 Pages) STMicroelectronics – Embedded temperature compensation

Register description
Figure 21: Interrupt events on INT_DRDY pin
LPS35HW
8.8
FIFO_CTRL (14h)
FIFO control register
Table 23: CTRL_REG3 (12h) register
7
6
5
4
3
2
F_MODE2 F_MODE1 F_MODE0 WTM4 WTM3 WTM2
1
WTM1
0
WTM0
FIFO mode selection. Default value: 000.
F_MODE[2:0]
Refer to Table 24: "FIFO mode selection"and Section 6: "FIFO" for additional details.
WTM[4:0]
FIFO watermark level selection.
F_MODE2
0
0
0
0
1
1
1
1
Table 24: FIFO mode selection
F_MODE1
F_MODE0
FIFO mode selection
0
0
Bypass mode
0
1
FIFO mode
1
0
Stream mode
1
1
Stream-to-FIFO mode
0
0
Bypass-to-Stream mode
0
1
Reserved
1
0
Dynamic-Stream mode
1
1
Bypass-to-FIFO mode
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