LPS35HW Datasheet, PDF (25/48 Pages) STMicroelectronics – Embedded temperature compensation

LPS35HW
Master ST
Slave
Digital interfaces
Table 13: Transfer when master is receiving (reading) one byte of data from slave
SAD+ W
SUB
SR SAD+ R
NMAK SP
SAK
SAK
SAK DATA
Mast S
er
T
Slave
Table 14: Transfer when master is receiving (reading) multiple bytes of data from slave
SAD+
SU
S SAD+
W
B
RR
MA
MA
NMA S
K
K
K
P
SA
SA
K
K
SA DAT
KA
DAT
A
DAT
A
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other functions, it can hold the clock line, SCL LOW to force the transmitter into a
wait state. Data transfer only continues when the receiver is ready for another byte and
releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is
not able to receive because it is performing some real-time function) the data line must be
kept HIGH by the slave. The master can then abort the transfer. A LOW-to-HIGH transition
on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data
transfer must be terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes incrementing the register address, it is necessary to assert
the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1
while SUB(6-0) represents the address of the first register to be read.
In the presented communication format MAK is Master acknowledge and NMAK is no
master acknowledge.
6.4
SPI bus interface
The LPS35HW SPI is a bus slave. The SPI allows writing to and reading from the registers
of the device.The serial interface interacts with the outside world with 4 wires: CS, SPC,
SDI and SDO.
Figure 14: Read and write protocol
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and returns to high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC. Both the read
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