LPS35HW Datasheet, PDF (26/48 Pages) STMicroelectronics – Embedded temperature compensation

Digital interfaces
LPS35HW
register and write register commands are completed in 16 clock pulses or in multiples of 8
in the case of multiple read/write bytes. Bit duration is the time between two falling edges of
SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS
while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before the rising
edge of CS.bit0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the
data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start
of bit 8.
bit1-7: address AD(6:0). This is the address field of the indexed register.
bit8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods are added. When the
IF_ADD_INC bit is 0, the address used to read/write data remains the same for every
block. When the IF_ADD_INC bit is 1, the address used to read/write data is incremented
at every block.
The function and the behavior of SDI and SDO remain unchanged.
6.5
SPI read
Figure 15: SPI read protocol
The SPI read command is performed with 16 clock pulses. The multiple byte read
command is performed by adding blocks of 8 clock pulses to the previous one.
bit0: READ bit. The value is 1.
bit1-7: address AD(6:0). This is the address field of the indexed register.
bit8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
bit16-...: data DO(...-8). Further data in multiple byte reads.
26/48
DocID029129 Rev 1