LPS35HW Datasheet, PDF (35/48 Pages) STMicroelectronics – Embedded temperature compensation

LPS35HW
Register description
every device. They allow correct behavior of the device and normally they should not be
changed. At the end of the boot process the BOOT bit is set again to ‘0’ by hardware. The
BOOT bit takes effect after one ODR clock cycle.
SWRESET is the software reset bit. The following device registers (INTERRUPT_CFG,
THS_P_L, THS_P_H, CTRL_REG1, CTRL_REG2, CTRL_REG3, FIFO_CTRL,
RIF_P_XL,RIF_P_L,RIF_P_H) are reset to the default value if the SWRESET bit is set to
'1'. SWRESET bit comes back to '0' by hardware.
The ONE_SHOT bit is used to start a new conversion when the ODR[2,0] bits in
CTRL_REG1(10h)are set to ‘000’. Writing a ‘1’ in ONE_SHOT triggers a single
measurement of pressure and temperature. Once the measurement is done, the
ONE_SHOT bit will self-clear, the new data are available in the output registers, and the
STATUS_REG bits are updated.
8.7
CTRL_REG3 (12h)
Control register 3 - INT_DRDY pin control register
Table 21: CTRL_REG3 (12h) register
7
6
5
4
3
2
1
0
INT_H_L PP_OD F_FSS5 F_FTH F_OVR DRDY INT_S2 INT_S1
INT_H_L Interrupt active-high/low. Default value: 0.(0: active high; 1: active low)
PP_OD
Push-pull/open drain selection on interrupt pads. Default value: 0. (0: push-pull; 1: open
drain)
F_FSS5 FIFO full flag on INT_DRDY pin. Default value: 0. (0: Disable; 1: Enable)
F_FTH
FIFO threshold (Watermark) status on INT_DRDY pin. Default value: 0. (0: Disable; 1:
Enable)
F_OVR
FIFO overrun interrupt on INT_DRDY pin. Default value: 0. (0: Disable; 1: Enable)
DRDY
Data-ready signal on INT_DRDY pin. Default value: 0. (0: Disable; 1: Enable)
INT_S[2:1]
Data signal on INT_DRDY pin control bits. Default value: 00. Refer to Table 22:
"Interrupt configurations".
INT_S2
0
0
1
1
INT_S1
0
1
0
1
Table 22: Interrupt configurations
INT_DRDY pin configuration
Data signal (in order of priority: PTH_DRDY or F_FTH or
F_OVR or F_FSSS5
Pressure high (P_high)
Pressure low (P_low)
Pressure low OR high
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