LAN91C100 Datasheet, PDF (77/101 Pages) SMSC Corporation – FEAST™ Fast Ethernet Controller

EISA BUS
SIGNAL
D0-D31
Table 5 - EISA 32 Bit Slave Signal Connections
LAN91C100 SIGNAL
NOTES
D0-D31
32 bit data bus. The bus byte(s) used to access the
device are a function of nBE0-nBE3:
nBE nBE nBE nBE
0
1
2
3
0
0
0
0 Double word access
0
0
1
1 Low word access
1
1
0
0 High word access
0
1
1
1 Byte 0 access
1
0
1
1 Byte 1 access
1
1
0
1 Byte 2 access
1
1
1
0 Byte 3 access
Not used = tri-state on reads, ignored on writes. Note that
nBE2 and nBE3 override the value of A1, which is tied
low in this application. Other combinations of nBE are
not supported by the LAN91C100. S/W drivers are not
anticipated to generate them.
nEX32
nNOWS
(optional
additional logic)
nLDEV
nLDEV is a totem pole output. nLDEV is active on valid
decodes of the LAN91C100's pins A15-A4 and AEN=0.
nNOWS is similar to nLDEV except that it should go
inactive on nSTART rising. nNOWS can be used to
request compressed cycles (1.5 BCLK long, nRD/nWR
will be 1/2 BCLK wide).
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES
BCLK
LCLK
EISA Bus Clock. Data transfer clock for DMA bursts.
nDAK<n>
nDATACS
DMA Acknowledge. Active during Slave DMA cycles.
Used by the LAN91C100 as nDATACS direct access to
data path.
nIORC
W/nR
Indicates the direction and timing of the DMA cycles.
High during LAN91C100 writes; low during LAN91C100
reads.
nIOWC
nCYCLE
Indicates slave DMA writes.
nEXRDY
nRDYRTN
EISA bus signal indicating whether a slave DMA cycle
will take place on the next BCLK rising edge, or should
be postponed. nRDYRTN is used as an input in the slave
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