LAN91C100 Datasheet, PDF (23/101 Pages) SMSC Corporation – FEAST™ Fast Ethernet Controller

I/O SPACE - BANK0
OFFSET
NAME
0
TRANSMIT CONTROL REGISTER
TYPE
READ/WRITE
SYMBOL
TCR
This register holds bits programmed by the CPU to control some of the protocol transmit options.
HIGH
BYTE
X
EPH
LOOP
STP
SQET
FDUPLX
MON_
CSN
NOCRC
X
0
0
0
0
X
0
LOW
BYTE
PAD_EN
FORCOL LOOP
TXENA
0
X
X
X
X
0
0
0
EPH_LOOP Internal loopback at the EPH
block. Serial data is looped back when set.
Defaults low. When EPH_LOOP is high, the
following transmit outputs are forced inactive:
TXD0-3=0h, TXEN100=TXEN=0, TXD=1. The
following external inputs are blocked:
CRS=CRS100=0,
COL=COL100=0,
RX_DV=RX_ER=0.
STP_SQET Stop transmission on SQET error.
If set, stops and disables transmitter on SQE
test error. Does not stop on SQET error and
transmits next frame if clear. Defaults low.
FDUPLX When set it enables full duplex
operation. This will cause frames to be received
if they pass the address filter regardless of the
source for the frame. When clear the node will
not receive a frame sourced by itself.
MON_CSN When set, the LAN91C100
monitors carrier while transmitting. It must see
its own carrier by the end of the preamble. If it
is not seen, or if carrier is lost during
transmission, the transmitter aborts the frame
without CRC and turns itself off. When this bit
is clear the transmitter ignores its own carrier.
Defaults low.
NOCRC Does not append CRC to transmitted
frames when set; allows software to insert the
desired CRC. Defaults to 0 (CRC inserted).
PAD_EN When set, the LAN91C100 will pad
transmit frames shorter than 64 bytes with 00.
Does not pad frames when reset.
FORCOL When set, the transmitter will force a
collision by not deferring deliberately. After the
collision this bit is reset automatically. This bit
defaults low to normal operation.
LOOP Loopback. General purpose output port
used to control the LBK pin. Typically used to
put the PHY chip in loopback mode.
TXENA Transmit enabled when set. Transmit
is disabled if clear. When the bit is cleared, the
LAN91C100 will complete the current
transmission before stopping. When stopping
due to an error, this bit is automatically cleared.
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