LAN91C100 Datasheet, PDF (5/101 Pages) SMSC Corporation – FEAST™ Fast Ethernet Controller

DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS
PQFP/TQFP
PIN NO.
184
NAME
Write/nRea
d
SYMBOL
W/nR
BUFFER
TYPE
I
DESCRIPTION
Input. Defines the direction of synchronous
cycles. Write cycles when high, read cycles
when low.
181
nVL Bus nVLBUS
Access
IP
Input. When low the LAN91C100
synchronous bus interface is configured for
VL Bus accesses. Otherwise the
LAN91C100 is configured for EISA DMA
burst accesses. Does not affect the
asynchronous bus interface.
105
Local Bus LCLK
Clock
I
Input. Used to interface synchronous buses.
Maximum frequency is 50 MHz. Limited to
8.33 MHz for EISA DMA burst mode.
175
Asynchron- ARDY
ous Ready
OD16
Open drain output. ARDY may be used
when interfacing asynchronous buses to
extend accesses. Its rising (access
completion) edge is controlled by the XTAL1
clock and therefore asynchronous to the
host CPU or bus clock.
106
nSynchron- nSRDY
ous Ready
O16 Output. This output is used when
interfacing synchronous buses and
nVLBUS=0 to extend accesses. This signal
remains normally inactive, and its falling
edge indicates completion. This signal is
synchronous to the bus clock LCLK.
109
nReady
nRDYRTN
Return
I
Input. This input is used to complete
synchronous read cycles. In EISA burst
mode it is sampled on falling LCLK edges,
and synchronous cycles are delayed until it
is sampled high.
176
Interrupt
187-189
INT0-INT3
O24 Outputs. Only one of these interrupts is
selected to be used; the other three are tri-
stated. The selection is determined by the
value of INT SEL1-0 bits in the
Configuration Register.
5