LAN91C100 Datasheet, PDF (41/101 Pages) SMSC Corporation – FEAST™ Fast Ethernet Controller

I/O SPACE - BANK2
OFFSET
8 THROUGH Bh
8
NAME
DATA REGISTER
TYPE
READ/WRITE
SYMBOL
DATA
DATA
9
DATA
A
DATA
B
DATA
DATA REGISTER Used to read or write the
data buffer byte/word presently addressed by
the pointer register.
This register is mapped into two uni-directional
FIFOs that allow moving words to and from the
LAN91C100 regardless of whether the pointer
address is even, odd or dword aligned. Data
goes through the write FIFO into memory, and
is pre-fetched from memory into the read FIFO.
If byte accesses are used, the appropriate
(next) byte can be accessed through the Data
Low or Data High registers. The order to and
from the FIFO is preserved. Byte, word and
dword accesses can be mixed on the fly in any
order.
This register is mapped into two consecutive
word locations to facilitate double word move
operations regardless of the actual bus width
(16 or 32 bits). The DATA register is accessible
at any address in the 8 through Ah range, while
the number of bytes being transferred are
determined by A1 and nBE0-nBE3. The FIFOs
are 12 bytes each.
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