LAN91C100 Datasheet, PDF (4/101 Pages) SMSC Corporation – FEAST™ Fast Ethernet Controller

DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS
PQFP/TQFP
PIN NO.
NAME
148-159 Address
SYMBOL
A4-A15
BUFFER
TYPE
I
DESCRIPTION
Input. Decoded by the LAN91C100 to
determine accesses to its registers.
145-147 Address
A1-A3
I
Input. Used by the LAN91C100 for internal
register selection.
193
Address
AEN
Enable
I
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
160-163 nByte
Enable
nBE0-nBE3
I
Input. Used during LAN91C100 register
accesses to determine the width of the
access and the register(s) being accessed.
nBE0-nBE3 are ignored when nDATACS is
low (burst accesses) because 32 bit
transfers are assumed.
173-170,
168-166,
164,144,
142-139,
137-135,
133,
131-129,
127,126,
124,123,
121,118,
117,
115-112,
110
Data Bus
D0-D31
I/O24
Bidirectional. 32 bit data bus used to access
the LAN91C100's internal registers. Data
bus has weak internal pullups. Supports
direct connection to the system bus without
external buffering. For 16 bit systems, only
D0-D15 are used.
182
Reset
RESET
IS
Input. This input is not considered active
unless it is active for at least 100ns to filter
narrow glitches.
95
nAddress nADS
Strobe
IS
Input. Address strobe. For systems that
require address latching, the rising edge of
nADS indicates the latching moment for A1-
A15 and AEN. All LAN91C100 internal
functions of A1-A15, AEN are latched except
for nLDEV decoding.
183
nCycle
nCYCLE
I
Input. This active low signal is used to
control LAN91C100 synchronous bus
cycles.
4