LAN91C100 Datasheet, PDF (17/101 Pages) SMSC Corporation – FEAST™ Fast Ethernet Controller

Serial EEPROM Interface Block
This block is responsible for reading the serial
EEPROM upon hardware reset (or equivalent
command) and defining defaults for some key
registers. A write operation is also implemented
EEPROM
by this block which, under CPU command, will
program specific locations in the EEPROM.
This block is an autonomous state machine, and
it controls the LAN91C100's internal Data Bus
during active operation.
DATA BUS
ADDRESS
BUS
CONTROL
EEPROM
INTERFACE
BUS INTERFACE
TX
FIFO
TX
COMPL
FIFO
RX
FIFO
DMA
CSMA/CD
TRANSMIT
RECEIVE
WRITE
DATA
REG
READ
DATA
REG
ARBITER
MMU
DATA
ADDRESS
BUFFER RAM
FIGURE 3 - LAN91C100 INTERNAL BLOCK DIAGRAM WITH DATA PATH
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