LAN91C100 Datasheet, PDF (73/101 Pages) SMSC Corporation – FEAST™ Fast Ethernet Controller

VL BUS
SIGNAL
LCLK
nRESET
nBE0 nBE1
nBE2 nBE3
nADS
IRQn
D0-D31
nLDEV
VCC
GND
OPEN
Table 3 - VL Local Bus Signal Connections
LAN91C100
SIGNAL
NOTES
LCLK
RESET
nBE0 nBE1
nBE2 nBE3
nADS, nCYCLE
INTR0-INTR3
D0-D31
Local Bus Clock. Rising edges used for synchronous bus
interface transactions.
Connected via inverter to the LAN91C100.
Byte enables. Latched transparently by nADS rising edge.
Address Strobe is connected directly to the VL bus. nCYCLE
is created typically by using nADS delayed by one LCLK.
Typically uses the interrupt lines on the ISA edge connector
of VL bus.
32 bit data bus. The bus byte(s) used to access the device
are a function of nBE0-nBE3:
nLDEV
nRD, nWR
A1, nVLBUS
nDATACS
BE0 BE1 nBE BE3
2
0
0
0
0 Double word access
0
0
1
1 Low word access
1
1
0
0 High word access
0
1
1
1 Byte 0 access
1
0
1
1 Byte 1 access
1
1
0
1 Byte 2 access
1
1
1
0 Byte 3 access
n
Not used = tri-state on reads, ignored on writes. Note that
nBE2 and nBE3 override the value of A1, which is tied low
in this application.
nLDEV is a totem pole output. nLDEV is active on valid
decodes of A15-A4 and AEN=0.
UNUSED PINS
73