LAN91C100 Datasheet, PDF (74/101 Pages) SMSC Corporation – FEAST™ Fast Ethernet Controller

HIGH-END ISA MACHINES
On ISA machines, the LAN91C100 is accessed
as a 16 bit peripheral. No support for XT (8 bit
peripheral) is provided. The signal connections
are listed in the following table:
ISA BUS
SIGNAL
A1-A15
AEN
nIORD
nIOWR
IOCHRDY
RESET
A0
nSBHE
IRQn
D0-D15
Table 4 - High-End ISA Machines Signal Connections
LAN91C100 SIGNAL
NOTES
A1-A15
AEN
nRD
nWR
ARDY
RESET
nBE0
nBE1
INTR0-INTR3
D0-D15
Address bus used for I/O space and register decoding
Qualifies valid I/O decoding - enabled access when low
I/O Read strobe - asynchronous read accesses. Address
is valid before leading edge
I/O Write strobe - asynchronous write access. Address is
valid before leading edge. Data is latched on trailing edge
This signal is negated on leading nRD, nWR if
necessary. It is then asserted on CLK rising edge after
the access condition is satisfied.
16 bit data bus. The bus byte(s) used to access the
device are a function of nBE0 and nBE1:
nBE0
0
0
1
nBE1
0
1
0
D0-D7
Lower
Lower
Not Used
D8-D15
Upper
Not Used
Upper
nIOCS16
nLDEV buffered
Not used = tri-state on reads, ignored on writes.
nLDEV is a totem pole output. Must be buffered using an
open collector driver. nLDEV is active on valid decodes
of A15-A4 and AEN=0.
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