COM20051I Datasheet, PDF (72/74 Pages) SMSC Corporation – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

TXEN
nPULSE
nPULSE
(Internal
RXIN
t1
t9
t4
t3
t2
t5
t6
t7
t10
t11
t8
LAST
(400 nS BIT
Paramete
t1 nPULSE2 High to TXEN
t2 nPULSE1 Pulse
t3 nPULSE1
t4 nPULSE2 Low to nPULSE1
t5 nPULSE2 High
t6 nPULSE2 Low
t7 nPULSE2
t8 nPULSE2 High to TXEN
t9 (first rising edge on nPULSE2 after Last Bit
TXEN Low to First nPULSE1
t10 RXIN Pulse
t11 RXIN
min typ max units
0
50 nS
200*
nS
400*
nS
-25
25 nS
100*
nS
100*
nS
200*
nS
0
50 nS
650
750 nS
10 200*
nS
400*
nS
* t5,t6 = 2 x (crystal period) for clock frequencies other than
* t2,t7,t10 = 4 x (crystal period) for clock frequencies other than
* t3,t11 = 8 x (crystal period) for clock frequencies other than
** t9: For clock frequencies other than 20 MHz, t9 = 14 x (clock period) ±
This period applies to data of two consecutive
Note: Clock frequency for 5 Mbps is 40
FIGURE 28 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING
(These signals are to and from the differential driver or the cable)
SMSC DS – COM20051I
Page 72
Rev. 03/27/2000