COM20051I Datasheet, PDF (24/74 Pages) SMSC Corporation – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

Table 4 – Read Register Summary
REG ISTER M SB
READ
LS B
S TAT U S
RI
X
X
POR TEST RECON TMA
TA
DIAG .
S TAT U S
M Y-
NEW
R E C O N ^{D U P ID R C VAC T TO K E N E XC N A K TE N TID} N E X TID
X
AD D R E S S
AUTO -
PTR
R D D ATA _{IN C}
X
X
X
X
A9
A8
HIG H
AD D R E S S
PTR
LO W
A7
A6
A5
A4
A3
A2
A1
A0
D ATA
D7
D6
D5
D4
D3
D2
D1
D0
OFFSET
AD D R E S S
00
01
02
03
04
RESERVED
X
X
X
X
X
X
X
X
05
C O N FIG -
U R AT IO N
RESET CCHEN TXEN
ET1
ET2
BACK-
PLANE
SUB-
AD1
SUB-
AD0
06
TE N TID
T ID 7
T ID 6
T ID 5
T ID 4
T ID 3
T ID 2
T ID 1
T ID 0
N O D E ID
NID7 NID6
NID5 NID4 NID3
N ID 2
N ID 1
N ID 0
SETUP
P1M O D E
FOUR
NAKS
ET3
RCV_
ALL
CKP3
CKP2
CKP1
SLOW
ARB
07
NEXT ID
NXTID7 NXTID6 NXTID5 NXTID4 NXTID3 NXTID2 NXTID1 NXTID0
RESERVED
X
X
X
X
X
X
X
X
08
IR R
X
5MBS DEC3 DEC2 DEC1
EXT
IN T1
IN T 0
09
N O T E : T he S LO W A R B bit m ust be se t for 5 M bps ope ra tion.
SMSC DS – COM20051I
Page 24
Rev. 03/27/2000