COM20051I Datasheet, PDF (27/74 Pages) SMSC Corporation – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

particular node. Each node on the network must occupy a unique Node ID value at all times. The Duplicate ID bit of
the Diagnostic Status Register helps the user find a unique Node ID. Refer to the Initialization Sequence section for
further detail on the use of the DUPID bit. The microsequencer of the ARCNET core does not wake up until a Node
ID other than zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are
passed by this node, and no reconfigurations are caused by this node. Once a non-zero Node ID is placed into the
Node ID Register, the core wakes up but will not join the network until the TXEN bit of the Configuration Register is
set. While the Transmitter is disabled, the Receiver portion of the device is still functional and will provide the user
with useful information about the network. The Node ID Register defaults to the value 0000 0000 upon hardware
reset only.
Next ID Register (Location +07Hex)
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up accordingly
(please refer to the Configuration Register). The Next ID Register holds the value of the Node ID to which the
COM20051I will pass the token. When used in conjunction with the Tentative ID Register, the Next ID Register can
provide a complete network map. The Next ID Register is updated each time a node enters/leaves the network or
when a network reconfiguration occurs. Each time the microsequencer updates the Next ID Register, a New Next ID
interrupt is generated. This bit is cleared by reading the Next ID Register. Default value is 0000 0000 upon hardware
or software reset.
Status Register (Location +00Hex)
The ARCNET Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software
compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout
status was provided in bits 5 and 6 of the Status Register. In the COM20020, the COM20020-5, COM20010,
COM90C66, and the COM90C165, these bits exist in and are controlled by the Configuration Register. The Status
Register contents are defined as in Table 6, but are defined differently during the Command Chaining operation.
Please refer to the Command Chaining section for the definition of the Status Register during Command Chaining
operation. The Status Register defaults to the value 1XX1 0001 upon either hardware or software reset.
Diagnostic Status Register (Location +01Hex)
The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network or node
operation. Various combinations of these bits and the TXEN bit of the Configuration Register represent different
situations. All of these bits, except the Excessive NAK bit and the New Next ID bit, are reset to logic "0" upon
reading the Diagnostic Status Register or upon software or hardware reset. The EXCNAK bit is reset by the "POR
Clear Flags" command upon software or hardware reset. The Diagnostic Status Register defaults to the value 0000
000X upon either hardware or software reset.
Command Register (Location +01Hex)
Execution of commands are initiated by performing write operations to this register. Any combinations of written
data other than those listed in Table 8 are not permitted and may result in incorrect chip and/or network operation.
Address Pointer Registers (Location +02Hex, +03Hex)
These read/write registers are each 8-bits wide and are used for addressing the internal ARCNET RAM. New pointer
addresses should be written by first writing to the High Register and then writing to the Low Register because writing
to the Low Register loads the address. The contents of the Address Pointer High and Low Registers are undefined
upon hardware reset.
Configuration Register (Location +06Hex)
The Configuration Register is a read/write register which is used to configure the different modes of the ARCNET
core. The Configuration Register defaults to the value 0001 1000 upon hardware reset only.
Setup Register (Location +07Hex)
The Setup Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (see the
bit definitions of the Configuration Register). The Setup Register allows the user to change the network speed (data
rate) or the arbitration speed independently, invoke the Receive All feature, change the nPULSE1 driver type, and
reduce protocol timeouts by a factor of 3. The data rate may be slowed to 156.25 Kbps and/or the arbitration speed
may be slowed by a factor of two. The SLOWARB must be set to a 1 for the 5 Mbps operation. The Setup Register
defaults to the value 0000 0000 upon hardware reset only.
SMSC DS – COM20051I
Page 27
Rev. 03/27/2000