COM20051I Datasheet, PDF (23/74 Pages) SMSC Corporation – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

ARCNET CORE FUNCTIONAL DESCRIPTION
MICROSEQUENCER
The ARCNET core contains an internal microsequencer which performs all of the control operations necessary to
carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two instruction
registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic.
The ARCNET core derives The Program Counter Clock and Instruction Execution Clock from the SYSTEM CLOCK.
If the system clock is 40 MHz the Program Counter Clock runs at 10 MHz and the Instruction Execution Clock runs at
5 MHz. If the System Clock is 20 MHz the above clocks run at 5 MHz and 2.5 MHz respectively. The microprogram
is stored in the ROM and the instructions are fetched and then placed into the instruction registers. One register
holds the op code, while the other holds the immediate data. Once the instruction is fetched, it is decoded by the
internal instruction decoder, at which point the ARCNET core proceeds to execute the instruction. When a no-op
instruction is encountered, the microsequencer enters a timed loop and the program counter is temporarily stopped
until the loop is complete. When a jump instruction is encountered, the program counter is loaded with the jump
address from the ROM. The ARCNET core contains an internal reconfiguration timer which interrupts the
microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of the
Diagnostic Status Register is set.
INTERNAL REGISTERS
The ARCNET core contains eight internal registers. Tables 4 and 5 illustrate the ARCNET core register map.
Reserved locations should not be accessed. All undefined bits are read as undefined and must be written as logic
"0".
Interrupt Mask Register (IMR) (Location +00Hex)
The ARCNET core is capable of generating an interrupt signal when certain status bits become true. A write to the
IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same
position as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a
particular position enables the corresponding interrupt. The Status bits capable of generating an interrupt include the
Receiver Inhibited bit, New Next ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit.
No other Status or Diagnostic Status bits can generate an interrupt.
The five maskable status bits are ANDed with their respective mask bits, and the results are ORed to produce the
interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset to logic "0", but will
reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been
cleared by this time. A RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK
interrupt is cleared when the "POR Clear Flags" command is issued. A New Next ID interrupt is cleared by reading
the New Next ID Register. The Interrupt Mask Register defaults to the value 0000 0000 upon hardware reset only.
Refer to Table 3.
Table 3 - Cleaning Interrupt Bit
INTERRUPT TYPE
CLEANING INTERRUPT BIT
RI
Issue "Enable Receive to Page Fnn" command
EXCNAK
Issue "Clean Flags" Command with "p" bit set
RECON
Issue "Clear Flags" Command with "r" bit set
New Next ID Read New Next ID Register
TA
Issue "Enable Transmit From Page Fnn"
Command
SMSC DS – COM20051I
Page 23
Rev. 03/27/2000