COM20051I Datasheet, PDF (26/74 Pages) SMSC Corporation – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

Interrupt Routing Register (Location +09HEX)
The Interrupt Routing Register (IRR) routes the interrupt generated by the ARCNET core to the appropriate 80C32
interrupt input (INT0 or INT1) or to one of the eight general purpose digital I/O ports (P1.0-1.7) of the 80C32. The
interrupt routing operates on a priority driven scheme where if two bits are enabled the highest priority always wins.
INT0 has highest priority followed by INT1 then EXT. The nINT0 and nINT1 bits route the interrupt signal to either the
nINT0 or nINT1 pin of the 80C32. The 80C32 nINT1 and nINT0 inputs are wire ANDed with the routed interrupt. This
allows the 80C32's interrupts to be used for more than one source. If many interrupts are being used in the system,
the COM20051I supports the use of an external interrupt controller to arbitrate simultaneous interrupts. External
interrupt controllers are supported by programming the EXT bit of the IRR. This will cause the interrupt signal to be
present on one of the Port 1 pins as programmed by Bits 3 - 5.
The 5 Mbps bit programs the ARCNET core to operate at a 5 Mbps data rate. The 5 Mbps bit causes the clock to the
ARCNET core to double its frequency from 20MHz to 40MHz. 5 Mbps operation requires the SLOWARB bit of the
SETUP register to be set. Failure to set the SLOWARB bit may result in errors when accessing the ARCNET buffer
RAM.
Table 6 - Interrupt Routing Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
6
5 Mbps Enable
5MBPS Causes the ARCNET core to operate at a 5 Mbps
data rate. Defaults to 0.
3-5
Port 1 Bit Assignment
DEC1 - 3
Selects one of the eight Port 1 bits to output the
interrupt on.
000 - P1.0
001 - P1.1
010 - P1.2
011 - P1.3
100 - P1.4
101 - P1.5
110 - P1.6
111 - P1.7
Defaults to 000 (P1.0).
2
External Interrupt Enable
EXT
Enables routing of the ARCNET interrupt onto on the
Port 1 pins. Defaults to 0.
1
Interrupt 1 Enable.
INT1
Enables wire Oring of the ARCNET interrupt with the
INT1 pin. Defaults to 0.
0
Interrupt 0
Enable.
INT0
Enables wire ORing if the ARCNET interrupt with the
INT0 pin. Defaults to 0.
Data Register (Location +04Hex)
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes. The data is
placed in or retrieved from the address location presently specified by the address pointer. The contents of the Data
Register are undefined upon hardware reset. In the case of READ operation, the Data Register is loaded with the
contents of ARCNET Core Internal RAM upon writing Address Pointer Low-only once.
Tentative ID Register (Location +07Hex)
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly
(please refer to the Configuration Register description). The Tentative ID Register can be used while the node is on-
line to build a network map of those nodes existing on the network. It minimizes the need for operator interaction with
the network. The node determines the existence of other nodes by placing a Node ID value in the Tentative ID
Register and waiting to see if the Tentative ID bit of the Diagnostic Status Register gets set. The network maps
developed by this method has only historical value, since nodes may join or depart from the network at any time.
When using the Tentative ID feature, a node cannot detect the existence of the next logical node to which it passes
the token. The Next ID Register will hold the ID value of that node. The Tentative ID Register defaults to the value
0000 0000 upon hardware reset only.
Node ID Register (Location +07Hex)
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly
(please refer to the Configuration Register). The Node ID Register contains the unique value which identifies this
SMSC DS – COM20051I
Page 26
Rev. 03/27/2000