COM20051I Datasheet, PDF (18/74 Pages) SMSC Corporation – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

SYSTEM DESCRIPTION
MICROCONTROLLER INTERFACE
COM20051I ARCNET network core contains 1K byte of RAM and 11 registers. The internal RAM is accessed via a
pointer-based scheme (refer to the Sequential Access Memory section), and the internal registers are accessed via
direct addressing. The ARCNET core bus interface is designed to be flexible so that it is independent of the 80C32
speed.
The COM20051I provides for no wait state arbitration via direct addressing to its internal registers and a pointer
based addressing scheme to access its internal RAM. Note that at 5 Mbps data rate, the internal arbiter must be
slowed down using the SLOWARB bit of the Setup Register. The pointer may be used in the auto-increment mode
for typical sequential buffer emptying or loading, or it can be taken out of the auto-increment mode to perform out of
sequence accesses to the RAM. The data within the RAM is accessed through the Data Register. Data being read
is prefetched from memory and placed into the Data Register for the microcontroller to read. During a write
operation, the data is stored in the Data Register and then written into memory. Whenever the pointer is loaded for
reads with a new value, data is immediately prefetched to prepare for the first read operation.
TRANSMISSION MEDIA INTERFACE
Figure 6 illustrates the COM20051I interface to the transmission media used to connect the node to the network.
Table 2 lists different types of cable which are suitable for ARCNET applications.1 The user may interface to the
cable of choice in one of three ways:
1 _{Please refer to TN7-5 - Cabling Guidelines for the COM20020 ULANC, available from SMSC, for recommended cabling}
distance, termination, and node count for ARCNET nodes.
Traditional Hybrid Interface
The Traditional Hybrid Interface is that which is used with previous ARCNET devices. The Hybrid Interface is
recommended if the node is to be placed in a network with other Hybrid-Interfaced nodes. The Traditional Hybrid
Interface is for use with nodes operating at 2.5 Mbps only. The transformer coupling of the Hybrid offers isolation for
the safety of the system and offers high Common Mode Rejection. The Traditional Hybrid Interface uses circuits like
SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20051I. The
COM20051I transmits a logic "1" by generating two 100nS non-overlapping negative pulses, nPULSE1 and
nPULSE2. Lack of pulses indicates a logic "0". The nPULSE1 and nPULSE2 signals are sent to the Hybrid, which
creates a 200nS dipulse signal on the medium. During reception, the 200nS dipulse appearing on the media is
coupled through the transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the
COM20051I. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". Typically, RXIN
pulses occur at multiples of 400nS. The COM20051I can tolerate distortion (bit jitter) of plus or minus 100nS and still
correctly capture and convert the RXIN pulses to NRZ format. Figure 8 illustrates the events which occur in
transmission or reception of data consisting of 1, 1, 0.
Backplane Configuration
The Backplane Configuration is recommended for cost-sensitive, short-distance applications like backplanes and
instrumentation. This mode is advantageous because it saves components, cost, and power.
SMSC DS – COM20051I
Page 18
Rev. 03/27/2000