COM20051I Datasheet, PDF (70/74 Pages) SMSC Corporation – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

t1
t2
t8
t5
t3
ALE
nPSEN
t9
t6
t7
t4
nWR
PORT 0
A0 - A7
t10
DATA O UT
PORT 2
A8 - A15 FROM DPH
P a ra me te r
t1 ALE Pulse Width
t2 ALE Low to nRD or nWR Low
t3 nRD or nWR High to ALE High
t4 WR Pulse Width
t5 Address Valid to ALE Low
t6 Data Hold after nWR
t7 Address Valid to nRD or nW R Low
t8 Address Hold after ALE Low
t9 Data Valid to nW R Transition
t10 Data Valid to nW R High
m in
typ
ma x units
85
137.5
22.5
275
7
12.5
120
27
2
287.5
nS
238.5 nS
102.5 nS
nS
nS
nS
nS
nS
nS
nS
FIGURE 26 – EXTERNAL DATA MEMORY WRITE CYCLE
SMSC DS – COM20051I
Page 70
Rev. 03/27/2000