EFR32FG12P432F Datasheet, PDF (99/183 Pages) Silicon Laboratories – EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet

4.1.25 USART SPI
SPI Master Timing
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
Table 4.53. SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
SCLK period ^{1 3 2}
t_SCLK
2*
—
t_HFPERCLK
CS to MOSI ^{1 3}
t_{CS_MO}
-14.5
—
SCLK to MOSI ^{1 3}
t_{SCLK_MO}
-8.5
—
MISO setup time ^{1 3}
t_{SU_MI}
IOVDD = 1.62 V
IOVDD = 3.0 V
92
—
42
—
MISO hold time ^{1 3}
t_{H_MI}
-10
—
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. t_HFPERCLK is one period of the selected HFPERCLK.
3. Measurement done with 8 pF output loading at 10% and 90% of V_DD (figure shows 50% of V_DD).
Max
Unit
—
ns
13.5
ns
8
ns
—
ns
—
ns
—
ns
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
MOSI
MISO
tCS_MO
tSCKL_MO
tSCLK
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
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