EFR32FG12P432F Datasheet, PDF (151/183 Pages) Silicon Laboratories – EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet

Alternate
Functionality
0-3
0: PF0
4-7
DBG_SWCLKTCK
0: PF1
DBG_SWDIOTMS
DBG_SWO
0: PF2
1: PB13
2: PD15
3: PC11
DBG_TDI
0: PF3
DBG_TDO
0: PF2
ETM_TCLK
ETM_TD0
ETM_TD1
0: PF8
1: PA5
2: PI2
3: PC6
0: PF9
1: PA6
2: PI3
3: PC7
0: PF10
1: PA7
2: PB6
3: PC8
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8 - 11
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
LOCATION
12 - 15 16 - 19
20 - 23
24 - 27
28 - 31
Description
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
Debug-interface
Serial Wire viewer
Output.
Note that this func-
tion is not enabled
after reset, and
must be enabled by
software to be
used.
Debug-interface
JTAG Test Data In.
Note that this func-
tion is enabled to
pin out of reset,
and has a built-in
pull up.
Debug-interface
JTAG Test Data
Out.
Note that this func-
tion is enabled to
pin out of reset.
Embedded Trace
Module ETM clock .
Embedded Trace
Module ETM data
0.
Embedded Trace
Module ETM data
1.
Rev. 1.0 | 146