EFR32FG12P432F Datasheet, PDF (127/183 Pages) Silicon Laboratories – EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet

6.6 QFN48 Sub-GHz Device Pinout
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Figure 6.6. QFN48 Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.7 GPIO Functionality Table or 6.8 Alternate Functionality Overview.
Table 6.6. QFN48 Sub-GHz Device Pinout
Pin Name
VSS
PF1
PF3
PF5
PF7
HFXTAL_N
Pins Description
0 Ground
2 GPIO (5V)
4 GPIO (5V)
6 GPIO (5V)
8 GPIO (5V)
10 High Frequency Crystal input pin.
Pin Name
PF0
PF2
PF4
PF6
RFVDD
HFXTAL_P
Pins Description
1 GPIO (5V)
3 GPIO (5V)
5 GPIO (5V)
7 GPIO (5V)
9 Radio power supply
11 High Frequency Crystal output pin.
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