EFR32FG12P432F Datasheet, PDF (120/183 Pages) Silicon Laboratories – EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet

6.3 BGA125 Sub-GHz Device Pinout
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
Figure 6.3. BGA125 Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.7 GPIO Functionality Table or 6.8 Alternate Functionality Overview.
Table 6.3. BGA125 Sub-GHz Device Pinout
Pin Name
Pins Description
PF3
A1 GPIO (5V)
PC5
A3 GPIO (5V)
PC0
A5 GPIO (5V)
PC9
A7 GPIO (5V)
DECOUPLE
Decouple output for on-chip voltage regu-
A9 lator. An external decoupling capacitor is
required at this pin.
VREGVDD A11 Voltage regulator VDD input
Pin Name
PF1
PC3
PC11
PC7
DVDD
VREGSW
Pins Description
A2 GPIO (5V)
A4 GPIO (5V)
A6 GPIO (5V)
A8 GPIO (5V)
A10 Digital power supply.
A12 DCDC regulator switching node
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