EFR32FG12P432F Datasheet, PDF (160/183 Pages) Silicon Laboratories – EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet

Alternate
Functionality
US2_CLK
US2_CS
US2_CTS
US2_RTS
US2_RX
US2_TX
US3_CLK
US3_CS
US3_CTS
US3_RTS
EFR32FG12 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
0-3
0: PA7
1: PA8
2: PA9
3: PI0
0: PA8
1: PA9
2: PI0
3: PI1
0: PA9
1: PI0
2: PI1
3: PI2
0: PI0
1: PI1
2: PI2
3: PI3
0: PA6
1: PA7
2: PA8
3: PA9
0: PA5
1: PA6
2: PA7
3: PA8
0: PD10
1: PD11
2: PD12
3: PD13
0: PD11
1: PD12
2: PD13
3: PD14
0: PD12
1: PD13
2: PD14
3: PD15
0: PD13
1: PD14
2: PD15
3: PI2
4-7
4: PI1
5: PI2
6: PI3
7: PB6
4: PI2
5: PI3
6: PB6
7: PB7
4: PI3
5: PB6
6: PB7
7: PB8
4: PB6
5: PB7
6: PB8
7: PB9
4: PI0
5: PI1
6: PI2
7: PI3
4: PA9
5: PI0
6: PI1
7: PI2
4: PD14
5: PD15
6: PI2
7: PI3
4: PD15
5: PI2
6: PI3
7: PB6
4: PI2
5: PI3
6: PB6
7: PB7
4: PI3
5: PB6
6: PB7
7: PB8
LOCATION
8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31
Description
8: PB7
9: PB8
10: PB9
11: PB10
12: PF0
13: PF1
14: PF3
15: PF4
16: PF5
17: PF6
18: PF7
19: PF8
20: PF9
21: PF10
22: PF11
23: PF12
24: PF13
25: PF14
26: PF15
27: PK0
28: PK1
29: PK2
30: PA5
31: PA6
USART2 clock in-
put / output.
8: PB8
9: PB9
10: PB10
11: PF0
12: PF1
13: PF3
14: PF4
15: PF5
16: PF6
17: PF7
18: PF8
19: PF9
20: PF10
21: PF11
22: PF12
23: PF13
24: PF14
25: PF15
26: PK0
27: PK1
28: PK2
29: PA5
30: PA6
31: PA7
USART2 chip se-
lect input / output.
8: PB9
9: PB10
10: PF0
11: PF1
12: PF3
13: PF4
14: PF5
15: PF6
16: PF7
17: PF8
18: PF9
19: PF10
20: PF11
21: PF12
22: PF13
23: PF14
24: PF15
25: PK0
26: PK1
27: PK2
28: PA5
29: PA6
30: PA7
31: PA8
USART2 Clear To
Send hardware
flow control input.
8: PB10
9: PF0
10: PF1
11: PF3
12: PF4
13: PF5
14: PF6
15: PF7
16: PF8
17: PF9
18: PF10
19: PF11
20: PF12
21: PF13
22: PF14
23: PF15
24: PK0
25: PK1
26: PK2
27: PA5
28: PA6
29: PA7
30: PA8
31: PA9
USART2 Request
To Send hardware
flow control output.
8: PB6
9: PB7
10: PB8
11: PB9
12: PB10
13: PF0
14: PF1
15: PF3
16: PF4
17: PF5
18: PF6
19: PF7
20: PF8
21: PF9
22: PF10
23: PF11
24: PF12
25: PF13
26: PF14
27: PF15
28: PK0
29: PK1
30: PK2
31: PA5
USART2 Asynchro-
nous Receive.
USART2 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
8: PI3
9: PB6
10: PB7
11: PB8
12: PB9
13: PB10
14: PF0
15: PF1
16: PF3
17: PF4
18: PF5
19: PF6
20: PF7
21: PF8
22: PF9
23: PF10
24: PF11
25: PF12
26: PF13
27: PF14
28: PF15
29: PK0
30: PK1
31: PK2
USART2 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
USART2 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
8: PB6
9: PB7
10: PB8
11: PB9
12: PB10
13: PB11
14: PJ14
15: PJ15
16: PC0
17: PC1
18: PC2
19: PC3
20: PC4
21: PC5
22: PF11
23: PF12
24: PF13
25: PF14
26: PF15
27: PK0
28: PK1
29: PK2
30: PD8
31: PD9
USART3 clock in-
put / output.
8: PB7
9: PB8
10: PB9
11: PB10
12: PB11
13: PJ14
14: PJ15
15: PC0
16: PC1
17: PC2
18: PC3
19: PC4
20: PC5
21: PF11
22: PF12
23: PF13
24: PF14
25: PF15
26: PK0
27: PK1
28: PK2
29: PD8
30: PD9
31: PD10
USART3 chip se-
lect input / output.
8: PB8
9: PB9
10: PB10
11: PB11
12: PJ14
13: PJ15
14: PC0
15: PC1
16: PC2
17: PC3
18: PC4
19: PC5
20: PF11
21: PF12
22: PF13
23: PF14
24: PF15
25: PK0
26: PK1
27: PK2
28: PD8
29: PD9
30: PD10
31: PD11
USART3 Clear To
Send hardware
flow control input.
8: PB9
9: PB10
10: PB11
11: PJ14
12: PJ15
13: PC0
14: PC1
15: PC2
16: PC3
17: PC4
18: PC5
19: PF11
20: PF12
21: PF13
22: PF14
23: PF15
24: PK0
25: PK1
26: PK2
27: PD8
28: PD9
29: PD10
30: PD11
31: PD12
USART3 Request
To Send hardware
flow control output.
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