SI5315 Datasheet, PDF (9/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
Table 3. AC Characteristics (Continued)
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min Typ Max Units
LVCMOS Output Pins
Rise/Fall Times
t_RF
CLOAD = 20 pf
—
25
—
ns
See Figure 2
LOSn Trigger Window
LOS_TRIG
From last CKINn  to
internal detection of LOSn
—
—
750 µs
Time to Clear LOL after LOS
Cleared
t_CLRLOL
LOS to  LOL
Assume Fold=Fnew,
Stable XA-XB reference
—
10
—
ms
PLL Performance
Output Clock Skew
Phase Change Due to
Temperature Variation
t_SKEW
of CKOUTn to CKOUTn
—
—
100 ps
t_TEMP Maximum phase change from
—
300
500
ps
–40 to +85 °C
Lock Time
t_LOCKHW RST with valid CKIN to LOL; —
1200
—
ms
BW = 100 Hz
Closed Loop Jitter Peaking
Jitter Tolerance
J_PK
J_TOL
— 0.05 0.1 dB
See 4.2.3. "Jitter Toler- ns pk-
ance" on page 18.
pk
Minimum Reset Pulse Width
t_RSTMIN
1
—
—
µs
Output Clock Initial Phase Step
t_{P_STEP}
During clock switch CKIN > 19.44
MHz
—
100
200
ps
Holdover Frequency Historical
Averaging Time
t_HISTAVG
—
6.7
—
sec
Holdover Frequency Historical
Delay Time
t_HISTDEL
— 26.2
—
ms
Spurious Noise
SP_SPUR
Max spur @ n x f3
(n > 1, n x f3 < 100 MHz)
—
–75
— dBc
Notes:
1. Assumes N3 does not equal 1. IF N3 = 1, CKN_DC = 50 µs.
2. Refers to Si5315A speed grade.
3. Refers to Si5315B speed grade.
Rev. 1.0
9